This section contains a brief description of the LEON3 SPARC V8 processor implementation developed by Gaisler Research, with an emphasis on information. LEON3 is a synthesizable VHDL model of a bit processor compliant with the SPARC V8 architecture. The processor is highly configurable, and particularly. LEON3 Processor. SPARC V8 instruction set with V8e extensions; Advanced 7- stage pipeline; Hardware multiply, divide and MAC units; High-performance, fully .
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The NGMP has the following on-chip functions:. This section and the subsequent subsections focus on the LEON processors as soft IP cores and summarise the main features of each processor version and the infrastructure with which the processor is packaged, referred to as a LEON distribution. This page was last edited on 23 Decemberat You have already rated this page, you can only rate it once! Archived copy as title Webarchive template wayback links Articles lacking reliable references from November All articles lacking reliable references Articles containing Spanish-language text Articles with Curlie links.
Airbus Defense and Space. The goals have been to detect and tolerate one error in any register without software intervention, and to suppress effects from Single Event Transient SET errors in combinational logic.
Please improve this by adding secondary or tertiary sources. BCC includes a small run-time with interrupt support and Pthreads library.
More information regarding these models can is available on the Aeroflex Gaisler website. Retrieved from ” https: It is elon3 to perform source-level symbolic debugging, either on a simulator or using real target hardware. LEON3 is also available under a low-cost commercial license, allowing it to be proceswor in any commercial application to a fraction of the cost of comparable IP cores.
The LEON4 processor has the following features:. It is thus possible to instantiate several processor cores in the same design with different configurations.
Up to 16 CPU can be used in a multiprocessing configuration. It has been designed for operation in the harsh space environment, and includes functionality to detect and correct single event upset SEU errors in all on-chip RAM memories. LEON3 is also available processod a proprietary license, allowing it to be used in proprietary applications.
The LEON3 processor has the following features:. Microprocessors are a core component of modern electronics and on-board computers do not escape this rule.
To maintain correct operation in the presence of SEUs, extensive error detection and error handling functions were needed. It features the following:.
It features the following: Branch prediction, 1-cycle load latency and a 32×32 orocessor results in a performance of 1. Aeroflex Gaisler – Device: Archived from the original PDF on Pre-synthesized FPGA programming files are also provided. The fault-tolerance is provided at design VHDL level, and does not require an SEU-hard semiconductor process, nor a custom cell library or special back-end tools.
SnapGear Linux is a full source package, containing kernel, libraries and application code for rapid development of embedded Linux systems. LEON has a dual license model: The model is highly configurable, and particularly suitable for system-on-a-chip SoC designs.
The full source code is available under the GNU GPL license, allowing free and unlimited use for research and education.
It is highly configurable, and elon3 designed for embedded applications with the following features on-chip:. While the LEON2 -FT design can be extended and re-used in other designs, its structure does not emphasise re-using parts of the design as building blocks or enable designers to easily incorporate new IP cores in the design.