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The input section is provided withLa double ended primary controller for resonant half-bridge ZVS zero voltage switching.
A voltage below 1. Output voltage regulation is obtained by modulating the operating frequency. Bias the pin between 1. Activating the zener causes the IC to shut down not latched. dxtasheet
An interface with the PFC controller xatasheet provided that enables to switch off the pre-regulator during fault conditions, such as OCP shutdown and DIS high, or during burst-mode operation. A capacitor connected from this pin to GND is charged and discharged by internal current generators programmed by the external network connected to pin 4 RFmin and determines the switching frequency of the converter.
All of the ground connections of the bias components should be tied to a track going to this pin and kept separate from any pulsed current return. Pin settings Pin functions continued Name Function Minimum oscillator frequency setting. This condition is allowed for a maximum time set at pin 2. Block Diagram and Schematic.
This pin, normally open, is intended for stopping the PFC controller, for protection purpose or during burst-mode operation. The comparator is provided with current hysteresis: A capacitor and a resistor are connected from this pin to GND to set both the maximum duration of an overcurrent condition before the IC stops switching and the delay after which the IC restarts switching.
Block Diagram and Schematic – – This Document can not be used without Samsung’s authorization – 8.
As the voltage on the pin exceeds 3. The IC will be soft-restarted as the voltage drops below 0. The chip restarts switching as the voltage exceeds the reference by 50 mV.
The voltage on the pin is top-limited by an internal zener. Internally the pin connects a comparator that, when the voltage on the pin exceeds 1. At start-up, to prevent uncontrolled inrush current, the switching frequency starts from a programmable maximum value and progressively decays until it reaches the steady-state value determined by the control loop. Supply Voltage of both the signal l659 of the IC and the low-side gate driver. Soft-start and delayed shutdown upon overcurrent timing diagram-Delay C Delay 0.
During UVLO, it is open. If the current keeps on building up despite this frequency increase, a second comparator referenced at 1. Oscillator’s internal block diagram. A mA mA Iq Residual consumption ? To close the feedback loop that regulates the converter output voltage by modulating the oscillator frequency, the phototransistor of an optocoupler will be connected to this pin through a resistor. High-side gate-drive floating ground. A current generator is ON as long as the voltage applied at the pin is below 1.
An R-C series connected from this pin to GND sets frequency shift at start-up to prevent excessive energy inrush soft-start. Sometimes a small bypass capacitor 0.
Try Findchips PRO for schematic diagram l The IC enables the designer to set the operating frequency range of the converter by means of an externally programmable datasjeet. The bootstrap capacitor connected between this pin and pin 14 OUT is fed by an internal synchronous bootstrap diode driven in-phase with the low-side gate-drive.
The value of this resistor will set the maximum operating frequency. A is kept always on.